1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to a configuration for achieving reduction of current consumption as well as high-speed operation of a semiconductor integrated circuit device including a logic gate constituted of a CMOS transistor.
2. Description of the Background Art
In the field of semiconductors, enhancement of integration and reduction of supply voltage are being promoted nowadays.
Since MOS transistors constituting an internal circuit have threshold voltage, the threshold voltage should be made smaller in order to secure a high-speed operation. However, a problem of a dramatic increase in the leakage current arises if the threshold voltage is decreased.
One scheme for solving this problem is a hierarchical power supply system. The hierarchical power supply system employed in a conventional semiconductor integrated circuit device will be described using FIG. 67.
In FIG. 67, a plurality of stages of CMOS inverters X1, X2, X3 . . . connected in cascade are shown as forming one example of an internal circuit.
CMOS inverters X1, X2 and X3 each include a PMOS transistor and an NMOS transistor. A main supply line L1, a sub-supply line L2, a main ground line L3 and a sub-ground line L4 for applying an operation supply voltage are arranged for inverters X1-X3.
A switching transistor T1 is placed between main supply line L1 and sub-supply line L2. Between main ground line L3 and sub-ground line L4, a switching transistor T2 is arranged.
Switching transistor T1 is brought to a conducting state in response to a hierarchical power supply control signal/.phi.c to electrically connect main supply line L1 and sub-supply line L2.
Switching transistor T2 is brought to the conducting state in response to a hierarchical power supply control signal .phi.c to electrically connect main ground line L3 and sub-ground line L4.
One operation supply node (a node receiving a higher potential) of inverters at the odd number stages X1, . . . each is connected to sub-supply line L2, and the other operation supply node (a node receiving a lower potential) is connected to main ground line L3.
One operation supply node (a node receiving a higher potential) of inverters at the even number stages X2 . . . each is connected to main supply line L1, and the other operation supply node (a node receiving a lower potential) is connected to sub-supply line L4.
Supply potential is applied to main supply line L1. Ground potential is applied to main ground line L3. Voltage of main supply line L1 is referred to as voltage Vcc, voltage of sub-supply line L2 is referred to as voltage SubVcc, voltage of main ground line L3 is referred to as voltage Vss, and voltage of sub-ground line L4 is referred to as voltage SubVss.
Referring to FIGS. 68 and 69, an operation of the conventional hierarchical power supply system shown in FIG. 67 is hereinafter described.
FIG. 68 illustrates a timing chart showing variation of supply potential in the conventional hierarchical power supply system shown in FIG. 67, and FIG. 69 is provided for describing voltage conditions of respective inverters X1, . . . in a standby cycle.
As shown in FIG. 69, inverters X1, . . . each include a PMOS transistor P1 and an NMOS transistor N1.
An input signal IN which is brought to an H level and an L level respectively in the standby cycle and an activate cycle is input to the internal circuit illustrated in FIG. 69. In the standby cycle, control signal .phi.c is set at the L level. Accordingly, switching transistors T1 and T2 are in OFF state in the standby cycle. In the active cycle, control signal .phi.c is set at the H level.
Upon transition from the active cycle to the standby cycle (at time t0 and t2 of FIG. 68), voltage SubVcc of sub-supply line L2 gradually decreases from the voltage Vcc level of main supply line L1 due to the load capacitor. On the other hand, voltage SubVss of sub-ground line L4 gradually changes to a higher level from voltage (ground supply voltage) Vss of main ground line L3 due to the load capacitor.
Upon transition from the standby cycle to the active cycle (at time t1 of FIG. 68), control signal .phi.c attains the H level. Accordingly, switching transistors T1 and T2 are brought to ON state. Voltage SubVcc of sub-supply line L2 is charged to the voltage Vcc level of main supply line L1. Voltage SubVss of sub-ground line L4. approaches to the voltage Vss level of main ground line L3.
Referring to FIG. 69, in the standby cycle, inverter X2 receives a signal of ground supply voltage Vss which is an inverted one of input signal IN. Accordingly, in inverter X2, PMOS transistor P1 attains ON state, and a connection node between PMOS transistor P1 and NMOS transistor N1 is set at voltage Vcc level of main supply line L1. Since NMOS transistor N1 receives voltage SubVcc of sub-ground line L4 higher than ground supply voltage Vss, the gate voltage becomes smaller than the source voltage. The leakage current in inverter X2 is thus restricted.
Inverter X3 receives a signal of voltage Vcc of main supply line L1. Accordingly, NMOS transistor N1 is brought to ON state, and a connection node between PMOS transistor P1 and NMOS transistor N1 is set at voltage Vss of main ground line L3. Since PMOS transistor P1 receives voltage SubVcc of sub-supply line L2 lower than voltage Vcc of main supply line L1, the gate voltage becomes higher than the source voltage. Accordingly, the leakage current in inverter X3 is restricted.
However, in the conventional hierarchical power supply system, as shown in FIG. 68, at the instant of transition from the standby cycle to the active cycle, switching transistors T1 and T2 are brought into ON state to cause a sudden voltage change of sub-supply line L2 and sub-ground line L4 (referred to as voltage drop).
Further, when switching transistor T1 and T2 attain ON state, the junction capacitance thereof causes voltage SubVcc of sub-supply line L2 to become a level slightly lower than voltage Vcc of main supply line L1 and causes voltage SubVss of sub-ground line L4 to keep a level slightly higher than voltage Vss of main ground line L3.
If the internal circuit operates in this state, a problem arises that an operation feature satisfying a desired condition cannot be obtained and it takes time to define an output from the internal circuit.
In addition, current consumption of a semiconductor integrated circuit device should be effectively decreased according to an operation timing.